diff -Naur u-boot-2010.09.orig/board/Marvell/dockstar/config.mk u-boot-2010.09.new/board/Marvell/dockstar/config.mk --- u-boot-2010.09.orig/board/Marvell/dockstar/config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2010.09.new/board/Marvell/dockstar/config.mk 2010-10-22 11:27:19.000000000 -0400 @@ -0,0 +1,28 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00600000 + +# Kirkwood Boot Image configuration file +KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg diff -Naur u-boot-2010.09.orig/board/Marvell/dockstar/dockstar.c u-boot-2010.09.new/board/Marvell/dockstar/dockstar.c --- u-boot-2010.09.orig/board/Marvell/dockstar/dockstar.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2010.09.new/board/Marvell/dockstar/dockstar.c 2010-10-22 11:27:19.000000000 -0400 @@ -0,0 +1,354 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include /* isspace */ +#include +#include "dockstar.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(DOCKSTAR_OE_VAL_LOW, + DOCKSTAR_OE_VAL_HIGH, + DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_TSMP9, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + +return 0; +} + +int misc_init_r() +{ + int __machine_arch_type; + char *str_arc_number = getenv("arcNumber"); + + if (str_arc_number) { + __machine_arch_type = simple_strtoul(str_arc_number, NULL, 10); + if (!__machine_arch_type) + __machine_arch_type = MACH_TYPE_DOCKSTAR; + } + + /* + * arch number of board + */ + gd->bd->bi_arch_number = __machine_arch_type; +} + +int dram_init(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = kw_sdram_bs(i); + } + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ + + +static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; +static uint8_t saved_blink_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; +static uint32_t gpio_pin[2] = {1 << (14 + STATUS_LED_GREEN), + 1 << (14 + STATUS_LED_RED)}; + +inline void switch_LED_on(uint8_t led) +{ + struct kwgpio_registers *gpio = (struct kwgpio_registers *)KW_GPIO1_BASE; + + writel(readl(&gpio->oe) & ~gpio_pin[led], &gpio->oe); + saved_state[led] = STATUS_LED_ON; +} + +inline void switch_LED_off(uint8_t led) +{ + struct kwgpio_registers *gpio = (struct kwgpio_registers *)KW_GPIO1_BASE; + + writel(readl(&gpio->oe) | gpio_pin[led], &gpio->oe); + saved_state[led] = STATUS_LED_OFF; +} + +void red_LED_on(void) +{ + switch_LED_on(STATUS_LED_RED); +} + +void red_LED_off(void) +{ + switch_LED_off(STATUS_LED_RED); +} + +void green_LED_on(void) +{ + switch_LED_on(STATUS_LED_GREEN); +} + +void green_LED_off(void) +{ + switch_LED_off(STATUS_LED_GREEN); +} + +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); +} + +void __led_toggle(led_id_t mask) +{ + if (STATUS_LED_RED == mask) { + (saved_state[STATUS_LED_RED] == STATUS_LED_ON) ? red_LED_off() : red_LED_on(); + } else if (STATUS_LED_GREEN == mask) { + (saved_state[STATUS_LED_GREEN] == STATUS_LED_ON) ? green_LED_off() : green_LED_on(); + } +} + +void __led_set(led_id_t mask, int state) +{ + if (STATUS_LED_RED == mask) { + (STATUS_LED_ON == state) ? red_LED_on() : red_LED_off(); + } else if (STATUS_LED_GREEN == mask) { + (STATUS_LED_ON == state) ? green_LED_on() : green_LED_off(); + } +} + +inline void switch_LED_blink_on(uint8_t led) +{ + struct kwgpio_registers *gpio = (struct kwgpio_registers *)KW_GPIO1_BASE; + + writel(readl(&gpio->blink_en) | gpio_pin[led], &gpio->blink_en); + saved_state[led] = STATUS_LED_ON; +} + +inline void switch_LED_blink_off(uint8_t led) +{ + struct kwgpio_registers *gpio = (struct kwgpio_registers *)KW_GPIO1_BASE; + + writel(readl(&gpio->blink_en) & ~gpio_pin[led], &gpio->blink_en); + saved_state[led] = STATUS_LED_OFF; +} + +void red_LED_blink_on(void) +{ + switch_LED_blink_on(STATUS_LED_RED); +} + +void red_LED_blink_off(void) +{ + switch_LED_blink_off(STATUS_LED_RED); +} + +void green_LED_blink_on(void) +{ + switch_LED_blink_on(STATUS_LED_GREEN); +} + +void green_LED_blink_off(void) +{ + switch_LED_blink_off(STATUS_LED_GREEN); +} + +void set_LED(char *szStatus) +{ + uint8_t led = -1; + uint8_t status = -1; + + /* Convert string to lowercase, max len 32 */ + int max = 32; + char *s = szStatus; + while (*s && max--) + *s++ = tolower(*s); + s = szStatus; + + /* Start with everything off */ + switch_LED_off(STATUS_LED_GREEN); + switch_LED_blink_off(STATUS_LED_GREEN); + switch_LED_off(STATUS_LED_RED); + switch_LED_blink_off(STATUS_LED_RED); + + if (szStatus == NULL) + { + red_LED_on(); + red_LED_blink_on(); + return; + } + + if ( strncmp(s, "green", 5) == 0 ) + { + s += 5; + led = STATUS_LED_GREEN; + } + else if ( strncmp(s, "orange", 6) == 0 ) + { + s += 6; + led = STATUS_LED_RED; + } + else if ( strncmp(s, "red", 3) == 0 ) + { + s += 3; + led = STATUS_LED_RED; + } + + if (led == -1 ) return; + + /* Skip Whitespace */ + while ( isspace(*s) ) s++; + + /* Commands like "green" or "orange" should just turn the light on */ + if ( *s == NULL || ( strncmp(s, "on", 2) == 0 ) ) + status = STATUS_LED_ON; + else if ( strncmp(s, "blink", 5) == 0 ) + status = STATUS_LED_BLINKING; + /* Unknown commands should turn the light off */ + else + status = STATUS_LED_OFF; + + if (status == STATUS_LED_OFF) + { + switch_LED_off(led); + switch_LED_blink_off(led); + } + else + { + switch_LED_on(led); + if (status == STATUS_LED_BLINKING) + switch_LED_blink_on(led); + } +} + + +void show_boot_progress (int val) +{ + if (val < 0) + set_LED( getenv("led_error") ); + + /* Ethernet Init */ + else if (val == 64) + set_LED( getenv("led_init") ); + + /* Passing control to an image */ + else if (val == 15) + set_LED( getenv("led_exit") ); +} + diff -Naur u-boot-2010.09.orig/board/Marvell/dockstar/dockstar.h u-boot-2010.09.new/board/Marvell/dockstar/dockstar.h --- u-boot-2010.09.orig/board/Marvell/dockstar/dockstar.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2010.09.new/board/Marvell/dockstar/dockstar.h 2010-10-22 11:27:19.000000000 -0400 @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __DOCKSTAR_H +#define __DOCKSTAR_H + +#define DOCKSTAR_OE_LOW (~(0)) +#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ +#define DOCKSTAR_OE_HIGH (~(0)) +#define DOCKSTAR_OE_VAL_HIGH (0) + +//#define DOCKSTAR_OE_HIGH (~(0x1 << 15)) /* Orange */ +//#define DOCKSTAR_OE_HIGH (~(0x1 << 14)) /* Green */ + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __DOCKSTAR_H */ diff -Naur u-boot-2010.09.orig/board/Marvell/dockstar/kwbimage.cfg u-boot-2010.09.new/board/Marvell/dockstar/kwbimage.cfg --- u-boot-2010.09.orig/board/Marvell/dockstar/kwbimage.cfg 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2010.09.new/board/Marvell/dockstar/kwbimage.cfg 2010-10-22 11:27:19.000000000 -0400 @@ -0,0 +1,162 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000000d # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +#DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +#DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Size, window disabled +DATA 0xFFD0150C 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD0151C 0x00000000 # DDR ODT Control (Low) +DATA 0xFFD01494 0x00030000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD01498 0x00000000 # CPU ODT Control +DATA 0xFFD0149C 0x0000e803 # DDR Initialization Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff -Naur u-boot-2010.09.orig/board/Marvell/dockstar/Makefile u-boot-2010.09.new/board/Marvell/dockstar/Makefile --- u-boot-2010.09.orig/board/Marvell/dockstar/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2010.09.new/board/Marvell/dockstar/Makefile 2010-10-22 11:27:19.000000000 -0400 @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dockstar.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -Naur u-boot-2010.09.orig/include/configs/dockstar.h u-boot-2010.09.new/include/configs/dockstar.h --- u-boot-2010.09.orig/include/configs/dockstar.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-2010.09.new/include/configs/dockstar.h 2010-10-22 11:27:42.000000000 -0400 @@ -0,0 +1,259 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_DOCKSTAR_H +#define _CONFIG_DOCKSTAR_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nMarvell-Dockstar/Pogoplug by Jeff Doozan" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_DOCKSTAR /* Machine type */ + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200,230400, 460800, 921600 } +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_SYS_LONGHELP +#define CONFIG_PREBOOT +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0xc0000 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */ + +/* + * Default environment variables + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "arcNumber=2097\0" \ + "mainlineLinux=yes\0" \ + "console=ttyS0,115200\0" \ + "usb_init=usb start\0" \ + "usb_device=0:1\0" \ + "usb_root=/dev/sda1\0" \ + "usb_rootfstype=ext2\0" \ + "usb_rootdelay=10\0"\ + \ + "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)\0"\ + "mtdids=nand0=orion_nand\0"\ + "partition=nand0,2\0"\ + \ + "bootcmd_pogo=fsload uboot-original-mtd0.kwb; go 0x800200\0" \ + \ + /* Zero the first bit at 0x800000 to clear any old image still in RAM after a warm reboot */\ + "usb_load_uimage=mw 0x800000 0 1; ext2load usb $usb_device 0x800000 /boot/uImage\0"\ + "usb_boot="\ + "if ext2load usb $usb_device 0x1100000 /boot/uInitrd; then"\ + " bootm 0x800000 0x1100000;"\ + "else"\ + " bootm 0x800000;"\ + "fi;\0"\ + \ + "set_bootargs_usb=setenv bootargs console=$console root=$usb_root rootdelay=$usb_rootdelay rootfstype=$usb_rootfstype $mtdparts\0" \ + "bootcmd_usb=run usb_init; run usb_load_uimage; run set_bootargs_usb; run usb_boot;\0" \ + \ + "led_init=green blinking\0" \ + "led_exit=green off\0" \ + "led_error=orange blinking\0" + + +#define CONFIG_BOOTCOMMAND "run bootcmd_usb; usb stop; run bootcmd_pogo; reset" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1 MiB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0 +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* + * File system + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +#define CONFIG_STATUS_LED +#define CONFIG_BOARD_SPECIFIC_LED + +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN // Fix + +#define STATUS_LED_GREEN 0 +#define STATUS_LED_RED 1 + +#define STATUS_LED_BIT STATUS_LED_GREEN +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ /4) + +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ /4) + +#define CONFIG_MISC_INIT_R + +#endif /* _CONFIG_DOCKSTAR_H */