/*
 * This file is auto-generated, do not modify!
 *
 * SPDX-License-Identifier: LGPL-2.1-or-later
 */

#pragma once
#include <fwupdplugin.h>
/**
 * FuRealtekMstDeviceDualBankMode:
 */
typedef enum {
    /**
     * FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_USER_ONLY:
     */
    FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_USER_ONLY,
    /**
     * FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_DIFF:
     */
    FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_DIFF,
    /**
     * FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_COPY:
     */
    FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_COPY,
    /**
     * FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_USER_ONLY_FLAG:
     */
    FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_USER_ONLY_FLAG,
}  FuRealtekMstDeviceDualBankMode;
#define FU_REALTEK_MST_DEVICE_DUAL_BANK_MODE_LAST 4
const gchar *fu_realtek_mst_device_dual_bank_mode_to_string(FuRealtekMstDeviceDualBankMode val) G_GNUC_CONST;
/**
 * FuRealtekMstDeviceFlashBank:
 */
typedef enum {
    /**
     * FU_REALTEK_MST_DEVICE_FLASH_BANK_BOOT:
     */
    FU_REALTEK_MST_DEVICE_FLASH_BANK_BOOT,
    /**
     * FU_REALTEK_MST_DEVICE_FLASH_BANK_USER1:
     */
    FU_REALTEK_MST_DEVICE_FLASH_BANK_USER1,
    /**
     * FU_REALTEK_MST_DEVICE_FLASH_BANK_USER2:
     */
    FU_REALTEK_MST_DEVICE_FLASH_BANK_USER2,
}  FuRealtekMstDeviceFlashBank;
#define FU_REALTEK_MST_DEVICE_FLASH_BANK_LAST 3
const gchar *fu_realtek_mst_device_flash_bank_to_string(FuRealtekMstDeviceFlashBank val) G_GNUC_CONST;
/**
 * FuRealtekMstReg:
 */
typedef enum {
    /**
     * FU_REALTEK_MST_REG_CMD_ATTR:
     */
    FU_REALTEK_MST_REG_CMD_ATTR = 0x60,
    /**
     * FU_REALTEK_MST_REG_ERASE_OPCODE:
     */
    FU_REALTEK_MST_REG_ERASE_OPCODE = 0x61,
    /**
     * FU_REALTEK_MST_REG_CMD_ADDR_HI:
     *
     * for commands
     */
    FU_REALTEK_MST_REG_CMD_ADDR_HI = 0x64,
    /**
     * FU_REALTEK_MST_REG_CMD_ADDR_MID:
     */
    FU_REALTEK_MST_REG_CMD_ADDR_MID = 0x65,
    /**
     * FU_REALTEK_MST_REG_CMD_ADDR_LO:
     */
    FU_REALTEK_MST_REG_CMD_ADDR_LO = 0x66,
    /**
     * FU_REALTEK_MST_REG_READ_OPCODE:
     */
    FU_REALTEK_MST_REG_READ_OPCODE = 0x6A,
    /**
     * FU_REALTEK_MST_REG_WRITE_OPCODE:
     */
    FU_REALTEK_MST_REG_WRITE_OPCODE = 0x6D,
    /**
     * FU_REALTEK_MST_REG_MCU_MODE:
     *
     * mode register address
     */
    FU_REALTEK_MST_REG_MCU_MODE = 0x6F,
    /**
     * FU_REALTEK_MST_REG_WRITE_FIFO:
     *
     * write data into write buffer
     */
    FU_REALTEK_MST_REG_WRITE_FIFO = 0x70,
    /**
     * FU_REALTEK_MST_REG_WRITE_LEN:
     *
     * number of bytes to write minus 1
     */
    FU_REALTEK_MST_REG_WRITE_LEN = 0x71,
    /**
     * FU_REALTEK_MST_REG_INDIRECT_LO:
     */
    FU_REALTEK_MST_REG_INDIRECT_LO = 0xF4,
    /**
     * FU_REALTEK_MST_REG_INDIRECT_HI:
     */
    FU_REALTEK_MST_REG_INDIRECT_HI = 0xF5,
}  FuRealtekMstReg;
