/*
 * This file is auto-generated, do not modify!
 *
 * SPDX-License-Identifier: LGPL-2.1-or-later
 */

#pragma once
#include <fu-input-stream.h>
/**
 * FuCcgxImageType:
 */
typedef enum {
    /**
     * FU_CCGX_IMAGE_TYPE_UNKNOWN:
     */
    FU_CCGX_IMAGE_TYPE_UNKNOWN,
    /**
     * FU_CCGX_IMAGE_TYPE_SINGLE:
     */
    FU_CCGX_IMAGE_TYPE_SINGLE,
    /**
     * FU_CCGX_IMAGE_TYPE_DUAL_SYMMETRIC:
     *
     * A/B runtime
     */
    FU_CCGX_IMAGE_TYPE_DUAL_SYMMETRIC,
    /**
     * FU_CCGX_IMAGE_TYPE_DUAL_ASYMMETRIC:
     *
     * A=bootloader (fixed) B=runtime
     */
    FU_CCGX_IMAGE_TYPE_DUAL_ASYMMETRIC,
    /**
     * FU_CCGX_IMAGE_TYPE_DUAL_ASYMMETRIC_VARIABLE:
     *
     * A=bootloader (variable) B=runtime
     */
    FU_CCGX_IMAGE_TYPE_DUAL_ASYMMETRIC_VARIABLE,
}  FuCcgxImageType;
#define FU_CCGX_IMAGE_TYPE_LAST 5
const gchar *fu_ccgx_image_type_to_string(FuCcgxImageType val) G_GNUC_CONST;
FuCcgxImageType fu_ccgx_image_type_from_string(const gchar *val) G_GNUC_CONST G_GNUC_NON_NULL(1);
/**
 * FuCcgxFwMode:
 */
typedef enum {
    /**
     * FU_CCGX_FW_MODE_BOOT:
     */
    FU_CCGX_FW_MODE_BOOT,
    /**
     * FU_CCGX_FW_MODE_FW1:
     */
    FU_CCGX_FW_MODE_FW1,
    /**
     * FU_CCGX_FW_MODE_FW2:
     */
    FU_CCGX_FW_MODE_FW2,
}  FuCcgxFwMode;
#define FU_CCGX_FW_MODE_LAST 3
const gchar *fu_ccgx_fw_mode_to_string(FuCcgxFwMode val) G_GNUC_CONST;
/**
 * FuCcgxPdResp:
 */
typedef enum {
    /**
     * FU_CCGX_PD_RESP_NO_RESPONSE:
     *
     * responses
     */
    FU_CCGX_PD_RESP_NO_RESPONSE,
    /**
     * FU_CCGX_PD_RESP_SUCCESS:
     */
    FU_CCGX_PD_RESP_SUCCESS = 0x02,
    /**
     * FU_CCGX_PD_RESP_FLASH_DATA_AVAILABLE:
     */
    FU_CCGX_PD_RESP_FLASH_DATA_AVAILABLE,
    /**
     * FU_CCGX_PD_RESP_INVALID_COMMAND:
     */
    FU_CCGX_PD_RESP_INVALID_COMMAND = 0x05,
    /**
     * FU_CCGX_PD_RESP_COLLISION_DETECTED:
     */
    FU_CCGX_PD_RESP_COLLISION_DETECTED,
    /**
     * FU_CCGX_PD_RESP_FLASH_UPDATE_FAILED:
     */
    FU_CCGX_PD_RESP_FLASH_UPDATE_FAILED,
    /**
     * FU_CCGX_PD_RESP_INVALID_FW:
     */
    FU_CCGX_PD_RESP_INVALID_FW,
    /**
     * FU_CCGX_PD_RESP_INVALID_ARGUMENTS:
     */
    FU_CCGX_PD_RESP_INVALID_ARGUMENTS,
    /**
     * FU_CCGX_PD_RESP_NOT_SUPPORTED:
     */
    FU_CCGX_PD_RESP_NOT_SUPPORTED,
    /**
     * FU_CCGX_PD_RESP_TRANSACTION_FAILED:
     */
    FU_CCGX_PD_RESP_TRANSACTION_FAILED = 0x0C,
    /**
     * FU_CCGX_PD_RESP_PD_COMMAND_FAILED:
     */
    FU_CCGX_PD_RESP_PD_COMMAND_FAILED,
    /**
     * FU_CCGX_PD_RESP_UNDEFINED:
     */
    FU_CCGX_PD_RESP_UNDEFINED,
    /**
     * FU_CCGX_PD_RESP_RA_DETECT:
     */
    FU_CCGX_PD_RESP_RA_DETECT = 0x10,
    /**
     * FU_CCGX_PD_RESP_RA_REMOVED:
     */
    FU_CCGX_PD_RESP_RA_REMOVED,
    /**
     * FU_CCGX_PD_RESP_RESET_COMPLETE:
     *
     * device specific events
     */
    FU_CCGX_PD_RESP_RESET_COMPLETE = 0x80,
    /**
     * FU_CCGX_PD_RESP_MESSAGE_QUEUE_OVERFLOW:
     */
    FU_CCGX_PD_RESP_MESSAGE_QUEUE_OVERFLOW,
    /**
     * FU_CCGX_PD_RESP_OVER_CURRENT_DETECTED:
     *
     * type-c specific events
     */
    FU_CCGX_PD_RESP_OVER_CURRENT_DETECTED,
    /**
     * FU_CCGX_PD_RESP_OVER_VOLTAGE_DETECTED:
     */
    FU_CCGX_PD_RESP_OVER_VOLTAGE_DETECTED,
    /**
     * FU_CCGX_PD_RESP_TYPE_C_CONNECTED:
     */
    FU_CCGX_PD_RESP_TYPE_C_CONNECTED,
    /**
     * FU_CCGX_PD_RESP_TYPE_C_DISCONNECTED:
     */
    FU_CCGX_PD_RESP_TYPE_C_DISCONNECTED,
    /**
     * FU_CCGX_PD_RESP_PD_CONTRACT_ESTABLISHED:
     *
     * pd specific events and asynchronous messages
     */
    FU_CCGX_PD_RESP_PD_CONTRACT_ESTABLISHED,
    /**
     * FU_CCGX_PD_RESP_DR_SWAP:
     */
    FU_CCGX_PD_RESP_DR_SWAP,
    /**
     * FU_CCGX_PD_RESP_PR_SWAP:
     */
    FU_CCGX_PD_RESP_PR_SWAP,
    /**
     * FU_CCGX_PD_RESP_VCON_SWAP:
     */
    FU_CCGX_PD_RESP_VCON_SWAP,
    /**
     * FU_CCGX_PD_RESP_PS_RDY:
     */
    FU_CCGX_PD_RESP_PS_RDY,
    /**
     * FU_CCGX_PD_RESP_GOTOMIN:
     */
    FU_CCGX_PD_RESP_GOTOMIN,
    /**
     * FU_CCGX_PD_RESP_ACCEPT_MESSAGE:
     */
    FU_CCGX_PD_RESP_ACCEPT_MESSAGE,
    /**
     * FU_CCGX_PD_RESP_REJECT_MESSAGE:
     */
    FU_CCGX_PD_RESP_REJECT_MESSAGE,
    /**
     * FU_CCGX_PD_RESP_WAIT_MESSAGE:
     */
    FU_CCGX_PD_RESP_WAIT_MESSAGE,
    /**
     * FU_CCGX_PD_RESP_HARD_RESET:
     */
    FU_CCGX_PD_RESP_HARD_RESET,
    /**
     * FU_CCGX_PD_RESP_VDM_RECEIVED:
     */
    FU_CCGX_PD_RESP_VDM_RECEIVED,
    /**
     * FU_CCGX_PD_RESP_SRC_CAP_RCVD:
     */
    FU_CCGX_PD_RESP_SRC_CAP_RCVD,
    /**
     * FU_CCGX_PD_RESP_SINK_CAP_RCVD:
     */
    FU_CCGX_PD_RESP_SINK_CAP_RCVD,
    /**
     * FU_CCGX_PD_RESP_DP_ALTERNATE_MODE:
     */
    FU_CCGX_PD_RESP_DP_ALTERNATE_MODE,
    /**
     * FU_CCGX_PD_RESP_DP_DEVICE_NONNECTED:
     */
    FU_CCGX_PD_RESP_DP_DEVICE_NONNECTED,
    /**
     * FU_CCGX_PD_RESP_DP_DEVICE_NOT_CONNECTED:
     */
    FU_CCGX_PD_RESP_DP_DEVICE_NOT_CONNECTED,
    /**
     * FU_CCGX_PD_RESP_DP_SID_NOT_FOUND:
     */
    FU_CCGX_PD_RESP_DP_SID_NOT_FOUND,
    /**
     * FU_CCGX_PD_RESP_MULTIPLE_SVID_DISCOVERED:
     */
    FU_CCGX_PD_RESP_MULTIPLE_SVID_DISCOVERED,
    /**
     * FU_CCGX_PD_RESP_DP_FUNCTION_NOT_SUPPORTED:
     */
    FU_CCGX_PD_RESP_DP_FUNCTION_NOT_SUPPORTED,
    /**
     * FU_CCGX_PD_RESP_DP_PORT_CONFIG_NOT_SUPPORTED:
     */
    FU_CCGX_PD_RESP_DP_PORT_CONFIG_NOT_SUPPORTED,
    /**
     * FU_CCGX_PD_RESP_HARD_RESET_SENT:
     *
     * not a response?
     */
    FU_CCGX_PD_RESP_HARD_RESET_SENT,
    /**
     * FU_CCGX_PD_RESP_SOFT_RESET_SENT:
     */
    FU_CCGX_PD_RESP_SOFT_RESET_SENT,
    /**
     * FU_CCGX_PD_RESP_CABLE_RESET_SENT:
     */
    FU_CCGX_PD_RESP_CABLE_RESET_SENT,
    /**
     * FU_CCGX_PD_RESP_SOURCE_DISABLED_STATE_ENTERED:
     */
    FU_CCGX_PD_RESP_SOURCE_DISABLED_STATE_ENTERED,
    /**
     * FU_CCGX_PD_RESP_SENDER_RESPONSE_TIMER_TIMEOUT:
     */
    FU_CCGX_PD_RESP_SENDER_RESPONSE_TIMER_TIMEOUT,
    /**
     * FU_CCGX_PD_RESP_NO_VDM_RESPONSE_RECEIVED:
     */
    FU_CCGX_PD_RESP_NO_VDM_RESPONSE_RECEIVED,
}  FuCcgxPdResp;
const gchar *fu_ccgx_pd_resp_to_string(FuCcgxPdResp val) G_GNUC_CONST;
/**
 * FuCcgxHpiVendorCmd:
 */
typedef enum {
    /**
     * FU_CCGX_HPI_VENDOR_CMD_GET_VERSION:
     *
     * get the version of the boot-loader
     */
    FU_CCGX_HPI_VENDOR_CMD_GET_VERSION = 0xB0,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_GET_SIGNATURE:
     *
     * value = 0, index = 0, length = 4;
     * data_in = 32 bit version
     * gsupposes to be 'CYUS' for normal firmware
     */
    FU_CCGX_HPI_VENDOR_CMD_GET_SIGNATURE = 0xBD,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_UART_GET_CONFIG:
     *
     * and 'CYBL' for Bootloader
     * retrieve the 16 byte UART configuration information
     */
    FU_CCGX_HPI_VENDOR_CMD_UART_GET_CONFIG = 0xC0,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_UART_SET_CONFIG:
     *
     * MS bit of value indicates the SCB index
     * length = 16, data_in = 16 byte configuration
     * update the 16 byte UART configuration information
     */
    FU_CCGX_HPI_VENDOR_CMD_UART_SET_CONFIG,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_SPI_GET_CONFIG:
     *
     * MS bit of value indicates the SCB index.
     * length = 16, data_out = 16 byte configuration information
     * retrieve the 16 byte SPI configuration information
     */
    FU_CCGX_HPI_VENDOR_CMD_SPI_GET_CONFIG,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_SPI_SET_CONFIG:
     *
     * MS bit of value indicates the SCB index
     * length = 16, data_in = 16 byte configuration
     * update the 16 byte SPI configuration  information
     */
    FU_CCGX_HPI_VENDOR_CMD_SPI_SET_CONFIG,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_I2C_GET_CONFIG:
     *
     * MS bit of value indicates the SCB index
     * length = 16, data_out = 16 byte configuration information
     * retrieve the 16 byte I2C configuration information
     */
    FU_CCGX_HPI_VENDOR_CMD_I2C_GET_CONFIG,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_I2C_SET_CONFIG:
     *
     * MS bit of value indicates the SCB index
     * length = 16, data_in = 16 byte configuration
     * update the 16 byte I2C configuration information
     */
    FU_CCGX_HPI_VENDOR_CMD_I2C_SET_CONFIG = 0xc5,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_I2C_WRITE:
     *
     * MS bit of value indicates the SCB index
     * length = 16, data_out = 16 byte configuration information
     * perform I2C write operation
     */
    FU_CCGX_HPI_VENDOR_CMD_I2C_WRITE,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_I2C_READ:
     *
     * value = bit0 - start, bit1 - stop, bit3 - start on idle,
     * bits[14:8] - target address, bit15 - scbIndex. length = 0 the
     * data  is provided over the bulk endpoints
     * value = bit0 - start, bit1 - stop, bit2 - Nak last byte,
     */
    FU_CCGX_HPI_VENDOR_CMD_I2C_READ,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_I2C_GET_STATUS:
     *
     * bit3 - start on idle, bits[14:8] - target address, bit15 - scbIndex,
     * length = 0. The data is provided over the bulk endpoints
     * value = bit0 - 0: TX 1: RX, bit15 - scbIndex, length = 3,
     */
    FU_CCGX_HPI_VENDOR_CMD_I2C_GET_STATUS,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_I2C_RESET:
     *
     * data_in = byte0: bit0 - flag, bit1 -  bus_state, bit2 - SDA state,
     * bit3 - TX underflow, bit4 - arbitration error, bit5 - NAK
     * bit6 - bus error,
     * byte[2:1] Data count remaining
     * the command cleans up the I2C state machine and frees the bus
     */
    FU_CCGX_HPI_VENDOR_CMD_I2C_RESET,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_SPI_READ_WRITE:
     *
     * value = bit0 - 0: TX path, 1: RX path; bit15 - scbIndex,
     * length = 0
     * the command starts a read / write operation at SPI
     */
    FU_CCGX_HPI_VENDOR_CMD_SPI_READ_WRITE = 0xCA,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_SPI_RESET:
     *
     * value = bit 0 - RX enable, bit 1 - TX enable, bit 15 -
     * scbIndex; index = length of transfer
     * the command resets the SPI pipes and allows it to receive new
     */
    FU_CCGX_HPI_VENDOR_CMD_SPI_RESET,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_SPI_GET_STATUS:
     *
     * request
     * value = bit 15 - scbIndex
     * the command returns the current transfer status
     */
    FU_CCGX_HPI_VENDOR_CMD_SPI_GET_STATUS,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_JTAG_ENABLE:
     *
     * the count will match the TX pipe status at SPI end
     * for completion of read, read all data
     * at the USB end signifies the end of transfer
     * value = bit 15 - scbIndex
     */
    FU_CCGX_HPI_VENDOR_CMD_JTAG_ENABLE = 0xD0,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_JTAG_DISABLE:
     */
    FU_CCGX_HPI_VENDOR_CMD_JTAG_DISABLE,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_JTAG_READ:
     */
    FU_CCGX_HPI_VENDOR_CMD_JTAG_READ,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_JTAG_WRITE:
     */
    FU_CCGX_HPI_VENDOR_CMD_JTAG_WRITE,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_GPIO_GET_CONFIG:
     */
    FU_CCGX_HPI_VENDOR_CMD_GPIO_GET_CONFIG = 0xD8,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_GPIO_SET_CONFIG:
     */
    FU_CCGX_HPI_VENDOR_CMD_GPIO_SET_CONFIG,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_GPIO_GET_VALUE:
     */
    FU_CCGX_HPI_VENDOR_CMD_GPIO_GET_VALUE,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_GPIO_SET_VALUE:
     */
    FU_CCGX_HPI_VENDOR_CMD_GPIO_SET_VALUE,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_PROG_USER_FLASH:
     *
     * The total space available is 512
     */
    FU_CCGX_HPI_VENDOR_CMD_PROG_USER_FLASH = 0xE0,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_READ_USER_FLASH:
     *
     * bytes this can be accessed by the user from USB. The flash
     * area address offset is from 0x0000 to 0x00200 and can be
     * written to page wise (128 byte)
     */
    FU_CCGX_HPI_VENDOR_CMD_READ_USER_FLASH,
    /**
     * FU_CCGX_HPI_VENDOR_CMD_DEVICE_RESET:
     */
    FU_CCGX_HPI_VENDOR_CMD_DEVICE_RESET = 0xE3,
}  FuCcgxHpiVendorCmd;
/**
 * FuCcgxPdRespReg:
 */
typedef enum {
    /**
     * FU_CCGX_PD_RESP_REG_DEVICE_MODE_ADDR:
     */
    FU_CCGX_PD_RESP_REG_DEVICE_MODE_ADDR,
    /**
     * FU_CCGX_PD_RESP_REG_BOOT_MODE_REASON:
     */
    FU_CCGX_PD_RESP_REG_BOOT_MODE_REASON,
    /**
     * FU_CCGX_PD_RESP_REG_SILICON_ID:
     */
    FU_CCGX_PD_RESP_REG_SILICON_ID,
    /**
     * FU_CCGX_PD_RESP_REG_BL_LAST_ROW:
     */
    FU_CCGX_PD_RESP_REG_BL_LAST_ROW = 0x04,
    /**
     * FU_CCGX_PD_RESP_REG_INTR_REG_ADDR:
     */
    FU_CCGX_PD_RESP_REG_INTR_REG_ADDR = 0x06,
    /**
     * FU_CCGX_PD_RESP_REG_JUMP_TO_BOOT_REG_ADDR:
     */
    FU_CCGX_PD_RESP_REG_JUMP_TO_BOOT_REG_ADDR,
    /**
     * FU_CCGX_PD_RESP_REG_RESET_ADDR:
     */
    FU_CCGX_PD_RESP_REG_RESET_ADDR,
    /**
     * FU_CCGX_PD_RESP_REG_ENTER_FLASH_MODE_ADDR:
     */
    FU_CCGX_PD_RESP_REG_ENTER_FLASH_MODE_ADDR = 0x0a,
    /**
     * FU_CCGX_PD_RESP_REG_VALIDATE_FW_ADDR:
     */
    FU_CCGX_PD_RESP_REG_VALIDATE_FW_ADDR,
    /**
     * FU_CCGX_PD_RESP_REG_FLASH_READ_WRITE_ADDR:
     */
    FU_CCGX_PD_RESP_REG_FLASH_READ_WRITE_ADDR,
    /**
     * FU_CCGX_PD_RESP_REG_GET_VERSION:
     */
    FU_CCGX_PD_RESP_REG_GET_VERSION = 0x10,
    /**
     * FU_CCGX_PD_RESP_REG_DBG_PD_INIT:
     */
    FU_CCGX_PD_RESP_REG_DBG_PD_INIT = 0x12,
    /**
     * FU_CCGX_PD_RESP_REG_U_VDM_CTRL_ADDR:
     */
    FU_CCGX_PD_RESP_REG_U_VDM_CTRL_ADDR = 0x20,
    /**
     * FU_CCGX_PD_RESP_REG_READ_PD_PROFILE:
     */
    FU_CCGX_PD_RESP_REG_READ_PD_PROFILE = 0x22,
    /**
     * FU_CCGX_PD_RESP_REG_EFFECTIVE_SOURCE_PDO_MASK:
     */
    FU_CCGX_PD_RESP_REG_EFFECTIVE_SOURCE_PDO_MASK = 0x24,
    /**
     * FU_CCGX_PD_RESP_REG_EFFECTIVE_SINK_PDO_MASK:
     */
    FU_CCGX_PD_RESP_REG_EFFECTIVE_SINK_PDO_MASK,
    /**
     * FU_CCGX_PD_RESP_REG_SELECT_SOURCE_PDO:
     */
    FU_CCGX_PD_RESP_REG_SELECT_SOURCE_PDO,
    /**
     * FU_CCGX_PD_RESP_REG_SELECT_SINK_PDO:
     */
    FU_CCGX_PD_RESP_REG_SELECT_SINK_PDO,
    /**
     * FU_CCGX_PD_RESP_REG_PD_CONTROL:
     */
    FU_CCGX_PD_RESP_REG_PD_CONTROL,
    /**
     * FU_CCGX_PD_RESP_REG_PD_STATUS:
     */
    FU_CCGX_PD_RESP_REG_PD_STATUS = 0x2c,
    /**
     * FU_CCGX_PD_RESP_REG_TYPE_C_STATUS:
     */
    FU_CCGX_PD_RESP_REG_TYPE_C_STATUS = 0x30,
    /**
     * FU_CCGX_PD_RESP_REG_CURRENT_PDO:
     */
    FU_CCGX_PD_RESP_REG_CURRENT_PDO = 0x34,
    /**
     * FU_CCGX_PD_RESP_REG_CURRENT_RDO:
     */
    FU_CCGX_PD_RESP_REG_CURRENT_RDO = 0x38,
    /**
     * FU_CCGX_PD_RESP_REG_CURRENT_CABLE_VDO:
     */
    FU_CCGX_PD_RESP_REG_CURRENT_CABLE_VDO = 0x3c,
    /**
     * FU_CCGX_PD_RESP_REG_DISPLAY_PORT_STATUS:
     */
    FU_CCGX_PD_RESP_REG_DISPLAY_PORT_STATUS = 0x40,
    /**
     * FU_CCGX_PD_RESP_REG_DISPLAY_PORT_CONFIG:
     */
    FU_CCGX_PD_RESP_REG_DISPLAY_PORT_CONFIG = 0x44,
    /**
     * FU_CCGX_PD_RESP_REG_ALTERNATE_MODE_MUX_SELECTION:
     */
    FU_CCGX_PD_RESP_REG_ALTERNATE_MODE_MUX_SELECTION = 0x45,
    /**
     * FU_CCGX_PD_RESP_REG_EVENT_MASK:
     */
    FU_CCGX_PD_RESP_REG_EVENT_MASK = 0x48,
    /**
     * FU_CCGX_PD_RESP_REG_RESPONSE_ADDR:
     */
    FU_CCGX_PD_RESP_REG_RESPONSE_ADDR = 0x7e,
    /**
     * FU_CCGX_PD_RESP_REG_BOOTDATA_MEMORY_ADDR:
     */
    FU_CCGX_PD_RESP_REG_BOOTDATA_MEMORY_ADDR = 0x80,
    /**
     * FU_CCGX_PD_RESP_REG_FWDATA_MEMORY_ADDR:
     */
    FU_CCGX_PD_RESP_REG_FWDATA_MEMORY_ADDR = 0xc0,
}  FuCcgxPdRespReg;
/**
 * FuCcgxHpiRegPart:
 */
typedef enum {
    /**
     * FU_CCGX_HPI_REG_PART_REG:
     *
     * register region
     */
    FU_CCGX_HPI_REG_PART_REG = 0,
    /**
     * FU_CCGX_HPI_REG_PART_DATA:
     *
     * data memory
     */
    FU_CCGX_HPI_REG_PART_DATA = 1,
    /**
     * FU_CCGX_HPI_REG_PART_FLASH:
     *
     * flash memory
     */
    FU_CCGX_HPI_REG_PART_FLASH = 2,
    /**
     * FU_CCGX_HPI_REG_PART_PDDATA_READ:
     *
     * read data memory
     */
    FU_CCGX_HPI_REG_PART_PDDATA_READ = 4,
    /**
     * FU_CCGX_HPI_REG_PART_PDDATA_WRITE:
     *
     * write data memory
     */
    FU_CCGX_HPI_REG_PART_PDDATA_WRITE = 8,
}  FuCcgxHpiRegPart;
/**
 * FuCcgxI2cDataConfig:
 */
typedef enum {
    /**
     * FU_CCGX_I2C_DATA_CONFIG_NONE:
     */
    FU_CCGX_I2C_DATA_CONFIG_NONE = 0,
    /**
     * FU_CCGX_I2C_DATA_CONFIG_STOP:
     */
    FU_CCGX_I2C_DATA_CONFIG_STOP = 1 << 0,
    /**
     * FU_CCGX_I2C_DATA_CONFIG_NAK:
     *
     * only for read
     */
    FU_CCGX_I2C_DATA_CONFIG_NAK = 1 << 1,
} G_GNUC_FLAG_ENUM FuCcgxI2cDataConfig;
/**
 * FuCcgxHpiDevReg:
 */
typedef enum {
    /**
     * FU_CCGX_HPI_DEV_REG_DEVICE_MODE:
     */
    FU_CCGX_HPI_DEV_REG_DEVICE_MODE = 0,
    /**
     * FU_CCGX_HPI_DEV_REG_BOOT_MODE_REASON:
     */
    FU_CCGX_HPI_DEV_REG_BOOT_MODE_REASON,
    /**
     * FU_CCGX_HPI_DEV_REG_SI_ID:
     */
    FU_CCGX_HPI_DEV_REG_SI_ID,
    /**
     * FU_CCGX_HPI_DEV_REG_SI_ID_LSB:
     */
    FU_CCGX_HPI_DEV_REG_SI_ID_LSB,
    /**
     * FU_CCGX_HPI_DEV_REG_BL_LAST_ROW:
     */
    FU_CCGX_HPI_DEV_REG_BL_LAST_ROW,
    /**
     * FU_CCGX_HPI_DEV_REG_BL_LAST_ROW_LSB:
     */
    FU_CCGX_HPI_DEV_REG_BL_LAST_ROW_LSB,
    /**
     * FU_CCGX_HPI_DEV_REG_INTR_ADDR:
     */
    FU_CCGX_HPI_DEV_REG_INTR_ADDR,
    /**
     * FU_CCGX_HPI_DEV_REG_JUMP_TO_BOOT:
     */
    FU_CCGX_HPI_DEV_REG_JUMP_TO_BOOT,
    /**
     * FU_CCGX_HPI_DEV_REG_RESET_ADDR:
     */
    FU_CCGX_HPI_DEV_REG_RESET_ADDR,
    /**
     * FU_CCGX_HPI_DEV_REG_RESET_CMD:
     */
    FU_CCGX_HPI_DEV_REG_RESET_CMD,
    /**
     * FU_CCGX_HPI_DEV_REG_ENTER_FLASH_MODE:
     */
    FU_CCGX_HPI_DEV_REG_ENTER_FLASH_MODE,
    /**
     * FU_CCGX_HPI_DEV_REG_VALIDATE_FW_ADDR:
     */
    FU_CCGX_HPI_DEV_REG_VALIDATE_FW_ADDR,
    /**
     * FU_CCGX_HPI_DEV_REG_FLASH_READ_WRITE:
     */
    FU_CCGX_HPI_DEV_REG_FLASH_READ_WRITE,
    /**
     * FU_CCGX_HPI_DEV_REG_FLASH_READ_WRITE_CMD:
     */
    FU_CCGX_HPI_DEV_REG_FLASH_READ_WRITE_CMD,
    /**
     * FU_CCGX_HPI_DEV_REG_FLASH_ROW:
     */
    FU_CCGX_HPI_DEV_REG_FLASH_ROW,
    /**
     * FU_CCGX_HPI_DEV_REG_FLASH_ROW_LSB:
     */
    FU_CCGX_HPI_DEV_REG_FLASH_ROW_LSB,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE1:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE1,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE2:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE2,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE3:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE3,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE4:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE4,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE5:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE5,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE6:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE6,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE7:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE7,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE8:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE8,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE9:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE9,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE10:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE10,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE11:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE11,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE12:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE12,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE13:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE13,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE14:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE14,
    /**
     * FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE15:
     */
    FU_CCGX_HPI_DEV_REG_ALL_VERSION_BYTE15,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_VERSION:
     */
    FU_CCGX_HPI_DEV_REG_FW2_VERSION,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE1:
     */
    FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE1,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE2:
     */
    FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE2,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE3:
     */
    FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE3,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE4:
     */
    FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE4,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE5:
     */
    FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE5,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE6:
     */
    FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE6,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE7:
     */
    FU_CCGX_HPI_DEV_REG_FW2_VERSION_BYTE7,
    /**
     * FU_CCGX_HPI_DEV_REG_FWBIN_LOC:
     */
    FU_CCGX_HPI_DEV_REG_FWBIN_LOC,
    /**
     * FU_CCGX_HPI_DEV_REG_FW1_BIN_LOC_LSB:
     */
    FU_CCGX_HPI_DEV_REG_FW1_BIN_LOC_LSB,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_BIN_LOC_MSB:
     */
    FU_CCGX_HPI_DEV_REG_FW2_BIN_LOC_MSB,
    /**
     * FU_CCGX_HPI_DEV_REG_FW2_BIN_LOC_LSB:
     */
    FU_CCGX_HPI_DEV_REG_FW2_BIN_LOC_LSB,
    /**
     * FU_CCGX_HPI_DEV_REG_PORT_ENABLE:
     */
    FU_CCGX_HPI_DEV_REG_PORT_ENABLE,
    /**
     * FU_CCGX_HPI_DEV_REG_LEN:
     */
    FU_CCGX_HPI_DEV_REG_LEN,
    /**
     * FU_CCGX_HPI_DEV_REG_RESPONSE:
     */
    FU_CCGX_HPI_DEV_REG_RESPONSE = 0x007e,
    /**
     * FU_CCGX_HPI_DEV_REG_FLASH_MEM:
     */
    FU_CCGX_HPI_DEV_REG_FLASH_MEM = 0x0200,
}  FuCcgxHpiDevReg;
/**
 * FuCcgxHpiRegSection:
 */
typedef enum {
    /**
     * FU_CCGX_HPI_REG_SECTION_DEV:
     *
     * device information
     */
    FU_CCGX_HPI_REG_SECTION_DEV,
    /**
     * FU_CCGX_HPI_REG_SECTION_PORT0:
     *
     * USB-PD Port 0
     */
    FU_CCGX_HPI_REG_SECTION_PORT0,
    /**
     * FU_CCGX_HPI_REG_SECTION_PORT1:
     *
     * USB-PD Port 1
     */
    FU_CCGX_HPI_REG_SECTION_PORT1,
    /**
     * FU_CCGX_HPI_REG_SECTION_ALL:
     */
    FU_CCGX_HPI_REG_SECTION_ALL,
}  FuCcgxHpiRegSection;
#define FU_CCGX_HPI_REG_SECTION_LAST 4
typedef struct {
  GByteArray *buf;
  guint refcount;
} FuStructCcgxMetadataHdr;

FuStructCcgxMetadataHdr *fu_struct_ccgx_metadata_hdr_ref(FuStructCcgxMetadataHdr *st) G_GNUC_NON_NULL(1);
void fu_struct_ccgx_metadata_hdr_unref(FuStructCcgxMetadataHdr *st) G_GNUC_NON_NULL(1);
G_DEFINE_AUTOPTR_CLEANUP_FUNC(FuStructCcgxMetadataHdr, fu_struct_ccgx_metadata_hdr_unref)
FuStructCcgxMetadataHdr *fu_struct_ccgx_metadata_hdr_new(void) G_GNUC_WARN_UNUSED_RESULT;
FuStructCcgxMetadataHdr *fu_struct_ccgx_metadata_hdr_parse_bytes(GBytes *blob, gsize offset, GError **error) G_GNUC_NON_NULL(1) G_GNUC_WARN_UNUSED_RESULT;
guint8 fu_struct_ccgx_metadata_hdr_get_fw_checksum(const FuStructCcgxMetadataHdr *st) G_GNUC_NON_NULL(1) G_GNUC_WARN_UNUSED_RESULT;
guint32 fu_struct_ccgx_metadata_hdr_get_fw_entry(const FuStructCcgxMetadataHdr *st) G_GNUC_NON_NULL(1) G_GNUC_WARN_UNUSED_RESULT;
guint16 fu_struct_ccgx_metadata_hdr_get_last_boot_row(const FuStructCcgxMetadataHdr *st) G_GNUC_NON_NULL(1) G_GNUC_WARN_UNUSED_RESULT;
guint32 fu_struct_ccgx_metadata_hdr_get_fw_size(const FuStructCcgxMetadataHdr *st) G_GNUC_NON_NULL(1) G_GNUC_WARN_UNUSED_RESULT;
guint16 fu_struct_ccgx_metadata_hdr_get_metadata_valid(const FuStructCcgxMetadataHdr *st) G_GNUC_NON_NULL(1) G_GNUC_WARN_UNUSED_RESULT;
guint32 fu_struct_ccgx_metadata_hdr_get_boot_seq(const FuStructCcgxMetadataHdr *st) G_GNUC_NON_NULL(1) G_GNUC_WARN_UNUSED_RESULT;
void fu_struct_ccgx_metadata_hdr_set_fw_checksum(FuStructCcgxMetadataHdr *st, guint8 value) G_GNUC_NON_NULL(1);
void fu_struct_ccgx_metadata_hdr_set_fw_entry(FuStructCcgxMetadataHdr *st, guint32 value) G_GNUC_NON_NULL(1);
void fu_struct_ccgx_metadata_hdr_set_last_boot_row(FuStructCcgxMetadataHdr *st, guint16 value) G_GNUC_NON_NULL(1);
void fu_struct_ccgx_metadata_hdr_set_fw_size(FuStructCcgxMetadataHdr *st, guint32 value) G_GNUC_NON_NULL(1);
void fu_struct_ccgx_metadata_hdr_set_metadata_valid(FuStructCcgxMetadataHdr *st, guint16 value) G_GNUC_NON_NULL(1);
void fu_struct_ccgx_metadata_hdr_set_boot_seq(FuStructCcgxMetadataHdr *st, guint32 value) G_GNUC_NON_NULL(1);

#ifndef __GI_SCANNER__
#define FU_STRUCT_CCGX_METADATA_HDR_OFFSET_FW_CHECKSUM 0x0
#define FU_STRUCT_CCGX_METADATA_HDR_OFFSET_FW_ENTRY 0x1
#define FU_STRUCT_CCGX_METADATA_HDR_OFFSET_LAST_BOOT_ROW 0x5
#define FU_STRUCT_CCGX_METADATA_HDR_OFFSET_FW_SIZE 0x9
#define FU_STRUCT_CCGX_METADATA_HDR_OFFSET_METADATA_VALID 0x16
#define FU_STRUCT_CCGX_METADATA_HDR_OFFSET_BOOT_SEQ 0x1C
#endif

#ifndef __GI_SCANNER__
#define FU_STRUCT_CCGX_METADATA_HDR_SIZE 0x20
#endif

#ifndef __GI_SCANNER__
#define FU_STRUCT_CCGX_METADATA_HDR_DEFAULT_METADATA_VALID 0x4359
#endif
